awesome-hdl

2019, An open source high level synthesis (HLS) tool using LLVM

c->verilog, DSP support

2003-?, GCC based c->verilog

2019, An experimental System-on-Chip with a custom compiler toolchain.

2016, C#, register assignment algorithms

specification to create a single representation of stimulus and test scenarios

asynchronous circuit/compiler tools

2025+, An HDL designed to help avoid common bugs while allowing low-level control through a Rust-like type system

Python-superset HDL for analog and mixed-signal IC design entry, part of the open-source ORDeC design platform

A language for hardcoding algorithms into FPGA hardware

2015+, Supports "timing-abstract" and "transaction-level design" methodologies; supported by proprietary and open-source tools

A refreshed Python toolbox for building complex digital hardware, 2018+

Compiler, simulator, and tools for the Bluespec Hardware Description Language.

Intermediate Language (IL) for Hardware Accelerator Generators, 2020+

A rule-based Meta HDL inspired by Bluespec, 2024+

Meta HDL, 2012+

Fast and cycle-accurate hardware simulation in CIRCT

firrtl to optimized C++ transpiler

VHDL compiler and simulator, IEEE 1076-2002, written in ADA

simulator

CIRCT IR to optimized C++ transpiler

Dependency management tool for hardware design projects.

Package manager and a set of build tools for HDL.

A lean dependency management and build system for hardware description projects.

Tool for processing of embedded Perl or Python scripts in Verilog source code.

CSR toolchain to generate RTL, UVM RAL models, document(html and markdown), IPXACT, c header from SystemRDL or IPXACT.

Code generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications

Javascript bit field diagram renderer

Javascript hierarchical schematic visualizer for HDLs

Javascript wave graph visualizer for RTL simulations

Javascript schematic visualizer

Plugin for sphinx documentation generator which adds schematic into html documentation.

Custom simulation visualization framework, available within the

2020+, LLVM / MLIR framework "Circuit IR Compilers and Tools"

2016-?, LLVM HW compiler## License

2016-?, Flexible Intermediate Representation for RTL

2017-?, A Multi-Language Synthesis and Simulation IR for Hardware Design

Low Level Hardware Description — A foundation for building hardware design tools

2019+, Framework for parsing and manipulating structural netlists in Python