awesome-riscv
github.com/suryakantamangaraj/awesome-riscv ↗RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.
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Technical Resources
- 2019 : A year of RISC-V and Open source siliconArticles
Year-in-review article covering the biggest RISC-V open-source silicon milestones of 2019.
- A Case for OS-Friendly Hardware AcceleratorsPapers and Publications
Paper arguing for OS-managed hardware accelerator interfaces.
- Accelerating Deep Convolutional Neural Networks Using Specialized HardwarePapers and Publications
Microsoft Research whitepaper on dedicated CNN hardware acceleration.
- Advanced Examples of Using ChiselTutorials
Wiki page with advanced Chisel hardware design examples using the Sodor RISC-V cores.
- A Hardware Accelerator for Tracing Garbage CollectionPapers and Publications
IEEE paper on custom hardware support for garbage collection in managed-runtime environments.
- AI Requires Many ApproachesPapers and Publications
Linley Group whitepaper on diverse hardware strategies for AI inference.
Open Source Toolchains
- AxeVerification and Testing Environment
Automatic black box testing.
- BOOM AttacksVerification and Testing Environment
BOOM Speculative Attacks.
- BRSIC-VDesign Environment
Browser-based RISC-V architecture design space exploration tool from Boston University.
- ChipyardDesign Environment
Framework for agile development of Chisel-based systems-on-chip.
- CHISELHDLs
Hardware Design Language that facilitates advanced circuit generation and design reuse in Scala.
- Chisel/FIRRTL Hardware Compiler FrameworkHDLs
Official website for the Chisel HDL and FIRRTL compiler framework.
Open Source Implementations
- bigPULPCores
Big version of the PULP platform with large cluster configurations for HPC workloads.
- biRISC-VCores
32-bit dual-issue in-order RISC-V CPU.
- BOOMCores
Berkeley Out-of-Order RISC-V Processor.
- CDL HardwareCores
Hardware designs in Cycle Description Language (CDL) targeting RISC-V.
- CV32E40PCores
OpenHW Group CORE-V CV32E40P RISC-V IP.
- CVA6Cores
6-stage, single-issue in-order RISC-V core maintained by the OpenHW Group.
Social Media
- Chisel UsersGoogle Groups
Community mailing list for users of the Chisel hardware design language.
- OSDForumForums
Open-source digital design forum covering RISC-V, FPGAs, and EDA topics.
- RISC-VReddit
Subreddit for RISC-V news, projects, and community discussion.
- RISC-VTelegram
Telegram group for real-time RISC-V community chat.
- RISC-V HW DevGoogle Groups
Official RISC-V hardware development mailing list.
- RISC-V ISA DevGoogle Groups
Official mailing list for RISC-V ISA specification development discussions.
Hardware
- HiFive1 Rev BEducational Boards
SiFive's Arduino-compatible RISC-V microcontroller board; an accessible entry point for bare-metal embedded programming.
- Milk-V DuoEducational Boards
Extremely low-cost ($5–$9) ultra-compact embedded Linux board based on a RISC-V + ARM dual-core SoC; great for IoT learning.
Showing a sample of 200 resources. View the full list on GitHub →